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Method and Apparatus for an SDRAM-Aware Router for Networks-on-Chip

Project ID: 1861-AP
Available for licensing

Background

An NoC (Network-on-Chip) is a scalable solution to complex on-chip interconnection problems. Since the performance of the whole system is sensitive to the performance of the memory subsystem, the memory subsystem managing the SDRAM is one of the most important components in 2D/3D NoC designs. However, it has been noted that the memory subsystem frequently underperforms due to the characteristic operation flows of an SDRAM and the dynamic accesses by other processing components.

Invention Description

This invention is a method and apparatus for an NoC router with an SDRAM-aware flow control and multi-scheduling scheme. Based on a priority-based arbitration, the router schedules competing packets to improve memory utilization and reduce memory latency. Moreover, it uses a multi-scheduling scheme performed by the multiple SDRAM-aware routers to help achieve better SDRAM performance and save on hardware cost of the NoC platform.

Benefits

Features

Market Potential/Applications

This invention can be applied in all NoCs and SoCs interfaced with on/off-chip SDRAM, circuit/packet based switches that schedule packets, and various SoCs interfaced with different kinds of memory.

UT Researcher

Zhigang Pan, Ph.D., Electrical and Computer Engineering, The University of Texas at Austin
Wooyoung Jang, Elec. & Computer Engineering, The University of Texas at Austin

OTC Contact Information

Jitendra Jain, Licensing Specialist
jjain@otc.utexas.edu
512-471-9055

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