High-performance, low-power delta-sigma analog-to-digital conversion

Project ID: 1702-AP
Available for licensing

Background

The Delta-Sigma ADC is an important building block for numerous electronic circuits today. In the market of high-performance data conversion, it is the ever-increasing thirst for wider bandwidths and lower power consumption without compromise in resolution that drives demand. Examples of high-performance Delta-Sigma ADC applications include cellular basestations, digital media receivers, automated test equipment, and medical imaging. This technology advances the state-of-the-art in switched-capacitor implementations by offering an increase in bandwidth without penalty in resolution, thus paving way for future products not available today

Two popular Delta-Sigma ADC structures are the cascade-of-resonators feedforward (CRFF) and cascade-of-integrators feedforward (CIFF) forms. CRFF has the the best quantization noise suppression performance, but requires the use of non-delaying integrators which can limit speed. CIFF does not have the non-delaying integrator requirement, but it pays a penalty in noise suppression performance. This technology offers a solution to this problem.

Invention Description

The loss of noise suppression performance in the CIFF structure stems from noise transfer function (NTF) zeros that do not lie on the unit-circle. These sub-optimal zeros translate into notches in the NTF that are shallow and inadequate to hold down the noise. The new technology has the ability to align these zeros on top of the unit-circle, similar to CRFF, but without using non-delaying integrators, and thus making it possible to simultaneously achieve high-speed and high-resolution. As a comparison, the peak signal-to-quanitzation noise ratio (SQNR) of similarly designed CIFF and CRFF modulators are 81.5dB and 87.5dB, respectively. With the new technology, the SQNR is 86.5dB, which is only 1dB shy of CRFF, makeing it attractive even in designs where maximum SQNR is desired due to its higher-speed potential

A prototype was designed and fabricated in 0.18um CMOS technology. Operating at 200-MS/s, the prototype achieves a peak SNR (signal-to-noise ratio) and SNDR (signal-to-noise-and-distortion ratio) of 75.3dB and 75.1dB, respectively, in a 12.5MHz signal band while consuming 89mW from a 1.8V supply. The figure of merit is 0.77pJ/conversion. Using 2.2 squared ENOB times the bandwidth as the performance metric, the prototype outperforms all IEEE-published low-pass discrete-time Delta-Sigma modulators to the best of our knowledge (as of Oct 2008).

Benefits

High performance
Low-power
Small area relative to performance
No calibration
No clock boosting
Flexible - can be clocked at different frequencies
Relatively lower sensitivity towards clock jitter compared to continuous-time implementations

Features

Has an SQNR advantage of 5-dB at 8x OSR with 4-b quantization as compared to the CIFF
Active area of just 0.8mm2

Market Potential/Applications

Cellular basestations, digital media receivers, automated test equipment, and medical imaging

Development Stage

Lab/bench prototype

UT Researcher

Jonathan W. Valvano, Ph.D., Electrical and Computer Engineering, The University of Texas at Austin
Robin M. Tsang, M.S., Electrical and Computer Engineering, The University of Texas at Austin

OTC Contact Information

Jitendra Jain, Licensing Specialist
jjain@otc.utexas.edu
512-471-9055